1. Field of the Invention
The present invention relates to devices for transmitting data stored in a RAM (random access memory), and more particularly to devices for transmitting data stored in a RAM after temporally writing the data to a FIFO (first input first output) memory, and method a thereof.
The present application for a RAM data transmitting apparatus using FIFO memory, is based on Korean Application Serial No. 39610/1995 which is incorporated herein by reference for all purposes.
2. Description of the Related Art
In general, a device such as a compact disk read only memory (CD-ROM) decoder is provided with an externally connecting RAM. For the RAM connected to the CD-ROM decoder, commonly referred to as a dynamic RAM, data applied from outside (data read from a compact disk) is processed by being temporally written and read as required when signed processing operations are to be performed on the data. That is, the CD-ROM decoder performs required actions such as error correction by reading data from outside which is written on a RAM and then writes the corrected data again on the RAM. The data written on the RAM after error correcting is accessed and processed by a host computer.
In accessing data written on a RAM (hereinafter called RAM data) by a host computer, an intervening first-in first-out memory (hereinafter, called FIFO) is generally used between the RAM and the host computer. In other words, when the access to the RAM data is required by the host computer, the RAM data to be transmitted is written on and then read out from the FIFO memory. Conventionally, this transmitting action is controlled by an empty flag and a full flag indicating the state of the FIFO. A controller for controlling the operation of the FIFO determines the state of the FIFO using these empty and full flags and applies request for RAM data transmitting to a RAM controller which controls the operation of the RAM. Then, according to the RAM data transmitting request signal received from the FIFO controller, the RAM controller writes the RAM data on the FIFO. The host computer reads the RAM data written on the FIFO until it receives an indication the FIFO is empty from the empty flag.
When a RAM data transmitting request signal is generated in response to the empty flag as mentioned above, the RAM controller causes RAM data to be written on the FIFO. When the RAM data is written on the entire contents of the FIFO, the full flag is generated and the RAM data transmitting request signal is stopped. At this time, the generation of the full flag is canceled when the host computer reads the data written on the FIFO, and the RAM data transmitting request signal is then generated again. When the host computer accesses the RAM data written on the FIFO at every time when the FIFO is full, the result is that the RAM data transmitting request signal occurs frequently, at a timing in proportion to the access times. However, since the RAM is being used in many ways, the frequent RAM data transmitting request signals inefficiently provide for few for the RAM chances to be used in the other ways. When the transmission of the RAM data is required when the FIFO becomes empty, the data access action of the host computer is blocked so long as the FIFO remains empty. Therefore, it is difficult to continuously access the data.